riscv.vim git · master

RISC-V assembly syntax for vim

vim riscv assembly · first commit 2019-02-01 · last commit 2024-12-31 (1 year ago) · synced 3 days ago · upstream: github.com/laurelmay/riscv.vim

Vim Script 87.9% Markdown 12.1%

git clone https://git.christianimmanuel.de/mirrors-forks/riscv.vim.gitwget https://git.christianimmanuel.de/mirrors-forks/riscv.vim/archive/riscv.vim.tar.gz

syntax/riscv.vim: Added Control Status Registers and Instructions used for interrupts

AlvaroMarques · 2019-11-03 09:46 · e7306dde5cd94240a5d05bfb7af8b31d090cffb2

 syntax/riscv.vim | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/syntax/riscv.vim b/syntax/riscv.vim
index 7cbf370..110fb7c 100644
--- a/syntax/riscv.vim
+++ b/syntax/riscv.vim
@@ -26,6 +26,7 @@ syntax keyword riscvRegister zero ra sp gp tp fp pc
 syntax keyword riscvRegister a0 a1 a2 a3 a4 a5 a6 a7
 syntax keyword riscvRegister t0 t1 t2 t3 t4 t5 t6
 syntax keyword riscvRegister s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11
+syntax keyword riscvRegister mepc mscratch mtvec mstatus mcause mie mpie mtval mip mpp
 
 " Assembler directives
 syntax match riscvDirective "\.data"
@@ -64,11 +65,11 @@ syntax keyword riscvInstruction scall sbreak
 " counters
 syntax keyword riscvInstruction rdcycle rdcycleh rdtime rdtimeh rdinstret rdinstreth
 " csr access
-syntax keyword riscvInstruction csrrw csrrs csrrc csrrwi csrrsi csrrci
+syntax keyword riscvInstruction csrrw csrrs csrrc csrrwi csrrsi csrrci csrr csrw
 " change level
 syntax keyword riscvInstruction ecall ebreak eret
 " trap redirect
-syntax keyword riscvInstruction mrts mrth hrts
+syntax keyword riscvInstruction mrts mrth hrts mret
 " interrupt
 syntax keyword riscvInstruction wfi
 " mmu