riscv.vim git · master

RISC-V assembly syntax for vim

vim riscv assembly · first commit 2019-02-01 · last commit 2024-12-31 (1 year ago) · synced 3 days ago · upstream: github.com/laurelmay/riscv.vim

Vim Script 87.9% Markdown 12.1%

git clone https://git.christianimmanuel.de/mirrors-forks/riscv.vim.gitwget https://git.christianimmanuel.de/mirrors-forks/riscv.vim/archive/riscv.vim.tar.gz

Remove duplicate RV64{I,M} lines

Kyle Laker · 2022-05-01 21:21 · b471644ee06698940f121d7a9af6a579a7390e85

 syntax/riscv.vim | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/syntax/riscv.vim b/syntax/riscv.vim
index cc15215..92f712d 100644
--- a/syntax/riscv.vim
+++ b/syntax/riscv.vim
@@ -355,18 +355,6 @@ syntax keyword riscvInstruction vrgatherei16.vv
 syntax keyword riscvInstruction vcompress.vm
 syntax match   riscvInstruction /\<vmv[1248]r\.v\>/
 
-
-" RV64I
-" load and store
-syntax keyword riscvInstruction lwu ld sd
-" shift
-syntax keyword riscvInstruction sllw srlw sraw slliw srliw sraiw
-" add / sub
-syntax keyword riscvInstruction addw subw addiw
-
-" RV64M
-syntax keyword riscvInstruction mulw divw divuw remw remuw
-
 " pseudo-instructions
 syntax keyword riscvInstruction li la lla lga
 syntax keyword riscvInstruction nop mv