riscv.vim git · master

RISC-V assembly syntax for vim

vim riscv assembly · first commit 2019-02-01 · last commit 2024-12-31 (1 year ago) · synced 3 days ago · upstream: github.com/laurelmay/riscv.vim

Vim Script 87.9% Markdown 12.1%

git clone https://git.christianimmanuel.de/mirrors-forks/riscv.vim.gitwget https://git.christianimmanuel.de/mirrors-forks/riscv.vim/archive/riscv.vim.tar.gz

Fix typo for saved registers

Kyle Laker · 2019-02-06 02:14 · 973d2e911c0a4121b7de48c7f69219077ee0276d

A misspelling of registers caused none of the sX registers to be
highlighted correctly.

 syntax/riscv.vim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/syntax/riscv.vim b/syntax/riscv.vim
index 916ddb0..70eb88e 100644
--- a/syntax/riscv.vim
+++ b/syntax/riscv.vim
@@ -27,7 +27,7 @@ syntax match   riscvRegister /\<x3[0-1]\>/
 syntax keyword riscvRegister zero ra sp gp tp fp pc
 syntax keyword riscvRegister a0 a1 a2 a3 a4 a5 a6 a7
 syntax keyword riscvRegister t0 t1 t2 t3 t4 t5 t6
-syntax keyword riscvReigster s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11
+syntax keyword riscvRegister s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11
 
 " Assembler directives
 syntax match riscvDirective "\.data"