Nimbin[12]?Mirrors & Forks / riscv.vim / commits / 24ad16a

riscv.vim git · master

RISC-V assembly syntax for vim

vim riscv assembly · first commit 2019-02-01 · last commit 2024-12-31 (1 year ago) · synced 3 days ago · upstream: github.com/laurelmay/riscv.vim

Vim Script 87.9% Markdown 12.1%
git clone https://git.christianimmanuel.de/mirrors-forks/riscv.vim.gitwget https://git.christianimmanuel.de/mirrors-forks/riscv.vim/archive/riscv.vim.tar.gz

Initial commit

Kyle Laker · 2019-02-01 20:51 · 24ad16ac498d2134dcff6f408ee5eb46f78e0fff

 LICENSE.md         |  24 ++++++++++++
 README.md          |   3 ++
 ftdetect/riscv.vim |   5 +++
 syntax/riscv.vim   | 112 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 144 insertions(+)

diff --git a/LICENSE.md b/LICENSE.md
new file mode 100644
index 0000000..c37e589
--- /dev/null
+++ b/LICENSE.md
@@ -0,0 +1,24 @@
+MIT License
+
+Copyright (c) 2019 Kyle Laker
+
+Permission is hereby granted, free of charge, to any person
+obtaining a copy of this software and associated documentation
+files (the "Software"), to deal in the Software without
+restriction, including without limitation the rights to use,
+copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..05c2a3e
--- /dev/null
+++ b/README.md
@@ -0,0 +1,3 @@
+# riscv.vim
+
+RISC-V syntax highlighting for Vim.
diff --git a/ftdetect/riscv.vim b/ftdetect/riscv.vim
new file mode 100644
index 0000000..64a364b
--- /dev/null
+++ b/ftdetect/riscv.vim
@@ -0,0 +1,5 @@
+" Vim ftdetect file
+" Language: RISC-V Assembly
+" Maintainer: Kyle Laker
+
+autocmd BufNewFile,BufReadPost *.S set filetype=riscv
diff --git a/syntax/riscv.vim b/syntax/riscv.vim
new file mode 100644
index 0000000..ae7ed19
--- /dev/null
+++ b/syntax/riscv.vim
@@ -0,0 +1,112 @@
+" Maintainer: Kyle Laker
+" Last Change: 2019 Feb 1
+
+if exists("b:current_syntax")
+    finish
+endif
+
+setlocal iskeyword+=-
+syntax case match
+
+syntax match  riscvComment /#.*/
+" Decimal numbers
+syntax match  riscvNumber  /\<[-]\?\d\+\>/
+" Hex numbers
+syntax match  riscvNumber  /\<-\?0\(x\|X\)[0-9a-fA-F]\+\>/
+syntax region riscvString  start=/"/ skip=/\\"/ end=/"/
+syntax match  riscvLabelColol /:/ contained
+syntax match  riscvLabel /\w\+:/ contains=risvLabelColon
+
+" Registers
+" Numbered registers
+syntax match riscvRegister /x([0-9]|[1-2][0-9]|3[0-1]/
+" Symbolic register names
+syntax keyword riscvRegister zero ra sp gp tp fp
+syntax match   riscvRegister /a[0-7]/
+syntax match   riscvRegister /t[0-6]/
+syntax match   riscvRegister /s[0-9]/
+syntax match   riscvRegister /s1[0-1]/
+
+" Assembler directives
+syntax match riscvDirective "\.data"
+syntax match riscvDirective "\.text"
+syntax match riscvDirective "\.byte"
+syntax match riscvDirective "\.asciiz"
+syntax match riscvDirective "\.word"
+syntax match riscvDirective "\.globl"
+syntax match riscvDirective "\.float"
+syntax match riscvDirective "\.double"
+syntax match riscvDirective "\.align"
+syntax match riscvDirective "\.string"
+
+" Instructions
+" loads
+syntax keyword riscvInstruction lb lh lw lbu lhu
+" stores
+syntax keyword riscvInstruction sb sh sw
+" shifts
+syntax keyword riscvInstruction sll slli srl srli sra srai
+" arithmetic
+syntax keyword riscvInstruction add addi sub lui auipc
+" logical
+syntax keyword riscvInstruction xor xori or ori and andi
+" compare
+syntax keyword riscvInstruction slt slti sltu sltiu
+" branches
+syntax keyword riscvInstruction beq bne blt bge bltu bgeu
+" jump & link
+syntax keyword riscvInstruction jal jalr
+" synch
+syntax keyword riscvInstruction fence
+syntax match   riscvInstruction "fence\.i"
+" system call
+syntax keyword riscvInstruction scall sbreak
+" counters
+syntax keyword riscvInstruction rdcycle rdcycleh rdtime rdtimeh rdinstret rdinstreth
+" csr access
+syntax keyword riscvInstruction csrrw csrrs csrrc csrrwi csrrsi csrrci
+" change level
+syntax keyword riscvInstruction ecall ebreak eret
+" trap redirect
+syntax keyword riscvInstruction mrts mrth hrts
+" interrupt
+syntax keyword riscvInstruction wfi
+" mmu
+syntax match   riscvInstruction "sfence\.vm"
+
+" M extension
+" multiply
+syntax keyword riscvInstruction mul mulh mulhsu mulhu
+" divide
+syntax keyword riscvInstruction div divu rem remu
+
+" A extension
+syntax match   riscvInstruction "lr\.w"
+syntax match   riscvInstruction "sc\.w"
+syntax match   riscvInstruction "amoswap\.w"
+syntax match   riscvInstruction "amoadd\.w"
+syntax match   riscvInstruction "amoxor\.w"
+syntax match   riscvInstruction "amoand\.w"
+syntax match   riscvInstruction "amoor\.w"
+syntax match   riscvInstruction "amomin\.w"
+syntax match   riscvInstruction "amomax\.w"
+syntax match   riscvInstruction "amominu\.w"
+syntax match   riscvInstruction "amomaxu\.w"
+
+" pseudo-instructions
+syntax keyword riscvInstruction nop li la mv
+syntax keyword riscvInstruction not neg negw
+syntax match   riscvInstruction "sext\.w"
+syntax keyword riscvInstruction seqz snez sltz sgtz
+syntax keyword riscvInstruction beqz bnez blez bgtz bgt ble bgtu bleu
+syntax keyword riscvInstruction j jr ret
+
+hi def link riscvComment        Comment
+hi def link riscvNumber         Number
+hi def link riscvString         String
+hi def link riscvRegister       Identifier
+hi def link riscvLabel          Label
+hi def link riscvDirective      Type
+hi def link riscvInstruction    Statement
+
+let b:current_syntax = "riscv"