riscv.vim git · master

RISC-V assembly syntax for vim

vim riscv assembly · first commit 2019-02-01 · last commit 2024-12-31 (1 year ago) · synced 3 days ago · upstream: github.com/laurelmay/riscv.vim

Vim Script 87.9% Markdown 12.1%

git clone https://git.christianimmanuel.de/mirrors-forks/riscv.vim.gitwget https://git.christianimmanuel.de/mirrors-forks/riscv.vim/archive/riscv.vim.tar.gz

Add ".asciiz" directive

Kyle Laker · 2022-04-30 19:43 · 0085268c1ec25bd5fb09a033c60669ad639b96bf

 syntax/riscv.vim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/syntax/riscv.vim b/syntax/riscv.vim
index 1471212..303802c 100644
--- a/syntax/riscv.vim
+++ b/syntax/riscv.vim
@@ -83,7 +83,7 @@ syntax keyword riscvCSRegister sedeleg sideleg
 
 " Assembler directives
 syntax keyword riscvDirective .align .ascii .file .globl .local .comm .common .ident
-syntax keyword riscvDirective .section .size .text .data .rodata .bss .string .asciz
+syntax keyword riscvDirective .section .size .text .data .rodata .bss .string .asciz .asciiz
 syntax keyword riscvDirective .equ .macro .endm .type .option .byte .2byte .half .short
 syntax keyword riscvDirective .4byte .word .long .8byte .dword .quad .skip
 syntax keyword riscvDirective .dtprelword .dtpreldword .sleb128 .uleb128